Acorn seemed to only have a few 'goes' at making a custom ASIC; see how ARM3 goes to great lengths to be compatible with MEMC, for example. For another example, IOEB wasn't integrated into an IOC version 2, it was a whole other chip (was it a PLA even)?
With hindsight you can design something better but I am guessing that at first they wanted to fit everything in cheap PLCCs with low pin count, and later wanted to get the maximum use out of the stock of chips they already had, for as long as they could.
As for Acorn spreading themselves across different platforms or becoming a consulting company, I'm not sure that would have done more for the world than what we got. I have my nostalgia goggles on, and selfishly, Acorn surviving but the Archimedes/Risc Pc line dying out earlier or not existing would have been a very great shame. I really appreciated the introduction to computing they gave me, and that meant the ARM and RISC OS.
26-bit became this massive sticking point but in the 80s a 64MiB address space must have seemed unfathomably massive - it's 1000x that of the 6502. The 68k only had 24 bits externally visible, so ARM's address space was 4x larger. And putting the flags in R15 allows for some pretty clever tricks. I don't think anyone predicted how fast RAM prices would drop.
I think RISC OS is the biggest sticking point. BBC compatibility was maybe a selling point for schools but the ARM was so much faster, you could just have shipped an upgraded !65Host and ditched OS_Byte/OS_Word and all the ridiculous weird gap modes. The competition had AmigaOS, which did a much better job on less capable hardware.
Here's my list hindsight-inspired things:
With hindsight you can design something better but I am guessing that at first they wanted to fit everything in cheap PLCCs with low pin count, and later wanted to get the maximum use out of the stock of chips they already had, for as long as they could.
As for Acorn spreading themselves across different platforms or becoming a consulting company, I'm not sure that would have done more for the world than what we got. I have my nostalgia goggles on, and selfishly, Acorn surviving but the Archimedes/Risc Pc line dying out earlier or not existing would have been a very great shame. I really appreciated the introduction to computing they gave me, and that meant the ARM and RISC OS.
26-bit became this massive sticking point but in the 80s a 64MiB address space must have seemed unfathomably massive - it's 1000x that of the 6502. The 68k only had 24 bits externally visible, so ARM's address space was 4x larger. And putting the flags in R15 allows for some pretty clever tricks. I don't think anyone predicted how fast RAM prices would drop.
I think RISC OS is the biggest sticking point. BBC compatibility was maybe a selling point for schools but the ARM was so much faster, you could just have shipped an upgraded !65Host and ditched OS_Byte/OS_Word and all the ridiculous weird gap modes. The competition had AmigaOS, which did a much better job on less capable hardware.
Here's my list hindsight-inspired things:
- Ditch ARX earlier and go look at AmigaOS, which didn't even have an MMU and yet had Unix-like things like shared libraries.
- Use APCS-R for all OS calls, even if they're implemented in assembler.
- As I said, implement BBC compatibility using emulation rather than making RISC OS an upgraded MOS.
- Add a small FIFO to IOC, and let MEMC/ARM kick off a single-line DMA burst to read/write it, reducing the need to PIO for floppy/serial transfers. Maybe this only makes sense once you have ARM3.
- In ARM3, do a more conventional 4-way cache (the cache was insanely over-specced IMO) and repurpose some of those massive CAMs for internal TLBs. Ignore the MEMC page table in ARM3 systems and have the ARM3 only request physical addresses from the bus.
- Again in ARM3, do a bus multiplier rather than the dual clock domain thing. I don't know how much design effort that would have saved, but 24MHz is not all that much slower than 25MHz, and from my limited understanding a fixed multiplier is easier all around.
- Reserve enough opcode space so that v4 features like 16-bit loads and stores, and sign-extended loads, could be added in a less awkward way.
- When moving to 32 bit, make instructions that write the PSR in R15 trap, allowing 26-bit code to be emulated efficiently in 32-bit mode.
- Ditch the 'x86 second processor' idea - but take advantage of the wider PC ecosystem earlier and faster. IOEB has a few ISA-like signals to talk to the super-IO chip - so put actual ISA slots in the A5000, and a PCI bus in the Risc Pc. Write ARM drivers for PC graphics and sound cards.
Statistics: Posted by edmundmk — Mon Dec 15, 2025 7:13 pm