No - the 6502 like most (but not all) processors can't tell "if it gets an answer" or not.As I understand it the 6512 CPU tries to get the start vector from address &FFFC and D and it keeps doing that until it gets an answer.
So it will stick FFFC (I haven't checked, as it's late, but it could do FFFD first - it'll be consistent but doesn't really matter) on the address bus, read junk from the data bus, stick FFFD on the address bus, read junk from the data bus, and then happily proceed to stick the junk it just read on the address bus, read the (likely more junk) from the data bus and assume that it's an instruction. If it is, then it'll do whatever it (randomly) says. If it's one of the invalid codes that locks up the CPU then that happens instead (this is easy to spot on the 6502 as the sync pin stops pulsing).
You should be able to see this on the logic analyser... but only the first few cycles will likely be "useful". One diagnostic trick for a flaky board is to drive the RESET line from a square-wave generator (via an open-collector transistor or similar to avoid conflicts & level issues) - the board then keeps repeating that first section and you can go around the bus lines around the board with a 'scope probe and check for the expected values on both busses, control lines, etc. (you can spam the break key for a similar effect, but it ties up a finger that could be holding another scope probe ...)
The oddness on the 16MHz is likely an artefact of the measurement setup.
Statistics: Posted by wiggy — Wed Oct 08, 2025 9:52 pm