(thanks BigEd for pointing me in this direction)
One thing that strikes me as unusual here is the use of indirect addressing to access the hardware, and that a page crossing occurs when accessing I/O space.So the LDA instruction will take 6 cycles, the last two of which will hit addresses that will cause clock stretching (&FD08 then &FE08).
I don't know if this is important, but it certainly seems deliberate, and will affectthe timing values returned. It may also be sensitive to the phase of the 1MHz clock on entry.
I'll ponder this some more when I have a bit more spare time.
Dave
One thing that strikes me as unusual here is the use of indirect addressing to access the hardware, and that a page crossing occurs when accessing I/O space.
Code:
&6042 b1 20 LDA (&20),Y ; control_register_address&6044 29 02 AND #&02 # &02 set if transmit interrupt&6046 d0 08 BNE &6050 ; transmit_interruptI don't know if this is important, but it certainly seems deliberate, and will affectthe timing values returned. It may also be sensitive to the phase of the 1MHz clock on entry.
I'll ponder this some more when I have a bit more spare time.
Dave
Statistics: Posted by hoglet — Thu Nov 21, 2024 9:38 am