That's not definitely something I would expect (in this context, both operators should behave the same).
It's possible what's happening here is that the ISE fitter is generating an initial seed from some kind of a digest of the VHDL, and that what should be a cosmetic change results in a different seed, which just happens to give a better fit (in both cases).
Could you upload a complete example (i.e. the xise/vhd/ucf files you are using) so I can try this out for myself?
Edit: Oh, and is it intentional that the (!RnW & Phi2 & GenBankSel[6] & WP[6]) is missing in both cases?
Dave
It's possible what's happening here is that the ISE fitter is generating an initial seed from some kind of a digest of the VHDL, and that what should be a cosmetic change results in a different seed, which just happens to give a better fit (in both cases).
Could you upload a complete example (i.e. the xise/vhd/ucf files you are using) so I can try this out for myself?
Edit: Oh, and is it intentional that the (!RnW & Phi2 & GenBankSel[6] & WP[6]) is missing in both cases?
Dave
Statistics: Posted by hoglet — Wed Aug 07, 2024 2:21 pm