Thanks, great explanationDRAM manufacturers specially designed the 7 bit 128 cycle, 2ms refresh types to maintain compatibility with existing systems that were designed for 4116 DRAM chips. For example, Z80 systems and other MPU systems that had support circuitry with only 7 bit refresh counters.
These DRAM have 7 rows for refresh purposes. The refresh address must be on the A0 to A6 address input pins. Generally the value on A7 is ignored during refresh, so can be logic low or high.
Internally they appear to be comprised of four groups of 64 rows X 256 columns, hence 64K. See the datasheet for the Mitsubishi M5K4164ANP. Or eight groups of 32 rows X 256 columns, see the datasheet for the Motorola MCM6665A.
As the technology of DRAM improved and was further developed, the refresh period was increased to 4ms (256 cycle types). But also other refresh methods became available such as hidden refresh, CAS before RAS, and on chip refresh counter circuitry (meaning there was no longer a need for the system to provide a refresh controller).
Mark
Statistics: Posted by mogwaay — Thu Apr 18, 2024 11:52 pm