AddedI would try this diagram, but there is no jed file for the gal 20v8 system
I have been experimenting with an extra 74LS74 as a 2 bit shift registers to delay the DISEN signal and got reasonable results. Not sure with what clock signal I have to clock it with to be perfect, probably propagation delay also messes exact timing up. Will update the circuit soon.
BTW, I used Galette as GAL assembler: https://github.com/simon-frankau/galette
Statistics: Posted by KGE — Sun Mar 10, 2024 10:26 am