ROMs aren't really "connected" to MEMC other than ROMCS - MEMC only sits (passively) on the address bus, not data bus.- The connections between the ROMS and MEMC seem fine.
The critical paths at this point are 1) ARM addresses -> latches -> ROMs and 2) ROM data -> ARM.
Usually it doesn't stop - check LA2 upwards. Normally what I see is that there's LA2..4 or so, but never as far as LA6/7 and until it's got that far, POST/POSTbox hasn't even started. Do you see ROMCS active?- With a scope on either the address or data bus, I can see that following reset there seems to be normal activity for a split second. Then it just stops.
Does this "run for a little bit then stop" behaviour suggest anything?
The keyboard isn't told to do anything until RISC OS starts so ignore that.
What frequency is HS/VS from VIDC? Should nominally be 15kHz/50Hz but it's not actually set up until a little way in to POST. Curiously, VIDC has not reset pin, so it can come up generating randomness, so if it looks like it's outputting weirdness, that'll just be because it's not been set up by POST yet.
Are you able to verify the ROMs using an external reader? Have you checked they're inserted in the right order?
Statistics: Posted by IanJeffray — Wed Nov 26, 2025 11:14 pm