You know when you do something you haven’t done for 40 years, which doesn’t look right and eventually you start to doubt your own sanity, well I’m at that point. ]( "Brick wall")
The following code from IanB’s version of the Econet module, that tests if an ADF10 is present: -Which using Zap, to disassemble the module, converts to this in BASIC Assembler: -
The registers for the MC6854 are as follows: -
When this code is run, these are what I see using an 8 channel 24Mz Logic Analyser, connected to the 8 BIT bus on the Unipod, with an ADF10 plugged in: -
And 8 is returned when reading SReg1.
Now this is where I’m getting confused, shouldn’t D0 be the least significant BIT, because to me the data bus looks mirrored or am I interpreting it incorrectly?
](http://www.stardot.org.uk/forums/images/smilies/eusa_wall.gif "Brick wall")
The following code from IanB’s version of the Econet module, that tests if an ADF10 is present: -
Code:
MOV r0, #2_11111000 ; TxRst, RxRst, FrDisc, TxDataSrvRq, RxDataSrvRq, -TIE, -RIE, -ACSTRB r0, CReg1MOV r0, #2_01111111 ; -RTS, ClrTxSt, ClrRxSt, TxLast, FrComp, Flag, 2Byte, PSESTRB r0, CReg2LDRB r1, SReg1TST r1, #2_11101101 ; IRQ, FC, TxU, -CTS, FlagDet, Loop, -SR2Rq, RDABNE nohardware ; Any of these BITs means no hardwareCode:
MOV R0, #&F8 ; TxRst, RxRst, FrDisc, TxDataSrvRq, RxDataSrvRq, -TIE, -RIE, -AC STRB R0, [R10,#0]MOV R0, #&7F ; -RTS, ClrTxSt, ClrRxSt, TxLast, FrComp, Flag, 2Byte, PSESTRB R0, [R10,#4]LDRB R1, [R10,#0]TST R1, #&ED ; IRQ, FC, TxU, -CTS, FlagDet, Loop, -SR2Rq, RDABNE nohardware ; Any of these BITs means no hardwareWhen this code is run, these are what I see using an 8 channel 24Mz Logic Analyser, connected to the 8 BIT bus on the Unipod, with an ADF10 plugged in: -
Now this is where I’m getting confused, shouldn’t D0 be the least significant BIT, because to me the data bus looks mirrored or am I interpreting it incorrectly?
Statistics: Posted by Drobell — Tue Oct 21, 2025 11:51 pm