Could give a whole new use case to NOP slides.It's mentioned in the data sheet.Even between instructions?One side effect of this is that single cycle instructions block interrupts. So a long stream of those = IRQs massively delayed.The data sheet also tells you put the TXS and TYS opcodes together to ensure there's no chance of getting an interrupt between them.This interrupt sequence [NMI] will begin with the first SYNC after a multiple-cycle opcode.
(SEI still takes 2 cycles, presumably to give an interrupt a chance to run in the CLI:SEI case.)
This does feel a bit questionable, but I suppose the average run of 1-cycle instructions won't be all that long. Probably fewer cycles in total than an indexed read-modify-write instruction/indexed indirect write/jsr/rts/etc.
--Tom
Statistics: Posted by Arx — Wed Sep 17, 2025 9:52 pm