8-bit acorn software: other • Re: IntegraB IBOS ROM Updates, Bug Reports and Feature Requests

Hi Jonathan,

Thanks for all the feedback...

[*]Implement new software Write Protect & Write Enable commands, *SRWP & *SRWE. These commands will only function on V2 hardware. They will generate a 'V2 Only' error if you attempt to run them on V1 hardware

Ah. Everything else (eg Plus1 SRAM Utils) uses *SRLOCK and SRUNLOCK.

The *SRWP & *SRWE commands have been present in the IBOS ROM since the early Computech days. They just never showed up in the *HELP and were never documented in the manual - basically because they didn't actually do anything meaning full. I suspect this is a feature that the original developers tried to implement, but subsequently dropped. For that reason, we just retained them.

[*]Will now display a maximum of 320K for V1 hardware, using two private RAM registers to store RAM presence of all 16 banks in 16K blocks. These registers can be set by *FX162,126,x (bit 0=bank 0, bit 7=bank 7) and *FX162,127,y (bit 0=bank 8, bit 7=bank 15)

I'll add that to the NVRAM page on the Wiki.

Thank you!

[*]Update *SRLOAD command with 'P' option that will Write Protect a previously Write Enabled bank following completion of the *SRLOAD operation. This avoids the need to do a separate *SRWP <id> afterwards. Works only on V2 hardware, will be silently ignored on V1 hardware.

Other systems (eg Plus1 SRAM Utils) uses 'L'ock and 'U'nlock.
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We kept away from using Lock and Unlock terminology, as this is used separately for locking and unlocking EEPROMs / Flash. IIRC, this is another case where the 'P'rotect functionality was already part implemented in older Computech versions of IBOS. As a very minimum, the facility existed to do this via bit 1 of OSWORD &43 function byte, but I'm fairly sure the 'P' option was also implemented in *SRLOAD. So again, we just retained that.

[*]Update *SRLOAD / *SRWRITE commands with 'T' option that will 'T'emporarily Write Enable the bank during the *SRLOAD / *SRWRITE operation. This avoids the need to do a separate *SRWE <id> (T) beforehand. Works only on V2 hardware, will be silently ignored on V1 hardware.

Plus1 SRAM Utils allows both L and U in the command, eg *SRLOAD fred 1 U L to Unlock, load, then Lock again.

Understood.

[*]Increase the buffer start address from PAGE to PAGE + &100, to avoid 'Bad Program' message using Q option to *SRLOAD or *SRSAVE ROM images when no BASIC program exists in memory.

Most other SRAM Utils use the top of memory at MEMTOP-&4000 (ie HIMEM-&4000), rather than the bottom of memory, specifically to get around this problem.

Understood. I did briefly look at doing something like that, but to avoid a more extensive rewrite of the code, the fix I implemented was a simple 1 byte (INX) change. Also, I think the buffer can actually be bigger than &4000 bytes, to cater for larger file copies when using Pseudo addressing mode, so it made sense not to limit the buffer in that way.

I hope all the error numbers are correct: link, link

LOL. I hope so too! We did try to be consistent.

Statistics: Posted by KenLowe — Tue Oct 08, 2024 12:04 am

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