I think you've lost a clock, or the Genlock connector isn't jumpered correctly.
(If you don't care about the reasoning behind this - skip down to the underlined text "QED" below)
SIRQ comes from the sound circuitry and is always derived from the system master clock (which is also the CPU clock).
VIRQ is more accurately called the "flyback" interrupt, or Vsync interrupt, and happens once per video frame. If the VIDC has no pixel clock, you'll have no video, no syncs, and crucially no VIRQ interrupt.
SIRQ is passing and the CPU is running code, which means the master clock is good and reaching VIDC. It also means the timer used for timing the interrupts is good, because if it wasn't then SIRQ would be failing too.
The VIDC data bus must be good too, because the "boop" sound (Wavesynth Beep) is sounding (the sound circuitry is inside VIDC). The sound data passes over the VIDC data bus.
VIDC register writes pass over that bus too -- and if the sound core is working, we can assume the data bus is probably working too.
Due to the unique way in which the VIDC is programmed, we can't say anything about the address bus, but that's an irrelevance because everything else works (tm).
QED: the video pixel clock is missing.
A5000s have a Genlock connector which is used to overlay video on an incoming video source e.g. PAL.
Check LK6. You should have two jumper caps fitted to it:
If you have those jumpers in place, remove them and make sure LK6 and the jumper caps are clean. Reinstall the jumper caps and check they're on the right pins. Finally if you have a multimeter, check for continuity between pins 1-2, then pins 3-4.
If that doesn't work then MUXCLK is gone:
(If you don't care about the reasoning behind this - skip down to the underlined text "QED" below)
SIRQ comes from the sound circuitry and is always derived from the system master clock (which is also the CPU clock).
VIRQ is more accurately called the "flyback" interrupt, or Vsync interrupt, and happens once per video frame. If the VIDC has no pixel clock, you'll have no video, no syncs, and crucially no VIRQ interrupt.
SIRQ is passing and the CPU is running code, which means the master clock is good and reaching VIDC. It also means the timer used for timing the interrupts is good, because if it wasn't then SIRQ would be failing too.
The VIDC data bus must be good too, because the "boop" sound (Wavesynth Beep) is sounding (the sound circuitry is inside VIDC). The sound data passes over the VIDC data bus.
VIDC register writes pass over that bus too -- and if the sound core is working, we can assume the data bus is probably working too.
Due to the unique way in which the VIDC is programmed, we can't say anything about the address bus, but that's an irrelevance because everything else works (tm).
QED: the video pixel clock is missing.
A5000s have a Genlock connector which is used to overlay video on an incoming video source e.g. PAL.
Check LK6. You should have two jumper caps fitted to it:
- one between pins 1 and 2, connecting MUXCLK to CKVIDC (selected VIDC clock to VIDC pixel clock in).
- one between pins 3 and 4, connecting SINK to ground.
If you have those jumpers in place, remove them and make sure LK6 and the jumper caps are clean. Reinstall the jumper caps and check they're on the right pins. Finally if you have a multimeter, check for continuity between pins 1-2, then pins 3-4.
If that doesn't work then MUXCLK is gone:
- Check for continuity from pin 1 of LK6 back to R406, then from R406 to IC400 pin 11 (74HC00).
- If you can't find R406, measure resistance from IC400 pin 11 to LK6 pin 1. Should be 68 Ohms or so due to R406.
- Check for continuity from pin 12 of IC400 (HC00) back to IOEB pin 85.
- If you have continuity but there's no life, check IC400 has 5V power between pins 14 and 7.
- If all the above pass, IC400 is probably dead, replace it.
Statistics: Posted by philpem — Tue Jan 16, 2024 12:31 am