Quick question...Values on the left hand side of this circuit are compromised as it's powered from a GPIO. If you don't mind burning the power statically, lower values will give better results. AC impedance remains 100R due to the capacitor (which is relatively small to allow it to unwind quickly once reverse charged).
Not quite an ideal circuit, though it works - that's why I designed the other one.
I note that you are using two switch circuits (3 & 4) to isolate the clock termination. I assume we could move both legs onto one switch, and free up the other switch? If so, I was then thinking we could use that spare switch to isolate a 5v supply to the data termination circuit instead of powering it from GPIO; thus allowing us to power the data termination from 5v, but still avoid burning power statically. Would that work, or have I misunderstood what you mean by burning power? What would the impact be on the sizing of the resistors and cap?
I'll pull together a schematic shortly.
Statistics: Posted by KenLowe — Sat Jun 15, 2024 6:22 pm